Row-based area-array I/O design planning in concurrent chip-package design flow

@article{Lee2011RowbasedAI,
  title={Row-based area-array I/O design planning in concurrent chip-package design flow},
  author={Ren-Jie Lee and Hung-Ming Chen},
  journal={16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)},
  year={2011},
  pages={837-842}
}
IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this article, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and… CONTINUE READING