Routability driven white space allocation for fixed-die standard-cell placement

  title={Routability driven white space allocation for fixed-die standard-cell placement},
  author={Xiaojian Yang and Bo-Kyung Choi and Majid Sarrafzadeh},
  booktitle={ACM International Symposium on Physical Design},
The use of white space in fixed-die standard-cell placement is an effective way to improve routability. In this paper, we present a white space allocation approach that dynamically assigns white space according to the congestion distribution of the placement. In the top-down placement flow, white space is assigned to congested regions using a smooth allocating function. A post allocation optimization step is taken to further improve placement quality. Experimental results show that the proposed… 

Figures and Tables from this paper

Routability-driven placement and white space allocation

A two-stage congestion-driven placement flow that replaces cells based on the wirelength weighted by congestion level to reduce the routing demands of congested regions and allocates appropriate amounts of white space according to a congestion map to significantly improve the routability of placements generated by other placement tools.

Flow-Based White Space Allocation for Fixed-Die Standard Cell Placement

  • Computer Science
  • 2002
A new global approach to white space allocation problem for xed die placement and an algorithm to allocate white space according to congestion distribution is proposed.

Routability-driven placement and white space allocation

We present a congestion-driven placement flow. First, we consider in the global placement stage the routing demand to replace cells in order to avoid congested regions. Then we allocate appropriate

Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs

A new direction/technique is proposed, called net overlapping removal, to optimize the routability during placement, and a Gaussian smoothing technique is proposed to handle the challenging macro porosity issue, arising in modern mixed-size designs with large macros.

Fast and Effective Placement Refinement for Routability

  • Yanheng ZhangC. Chu
  • Computer Science
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2013
The experimental results show that CROP effectively alleviates congestion for unroutable placement solutions in short runtimes for different placers.

Routability-driven Placement for Mixed-size Designs using Design-hierarchy and Pin Information

  • Prasun DattaS. Mukherjee
  • Computer Science
    2019 International Conference on Automation, Computational and Technology Management (ICACTM)
  • 2019
A routability-driven placement for large mixed-size standard cell designs is proposed and the implemented algorithms outperforms the other recent routable-driven placers on ICCAD 2012 benchmarks.

PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability

This article proposes an iterative approach to refine cell locations after global placement, where wirelength and routability are separately optimized in each iteration, and first moves cells to better locations to reduce wirelength.

Effective free space management for cut-based placement via analytical constraint generation

An enhancement to cut-based placement called analytic constraint generation (ACG), which utilizes an analytic engine to distribute available free space appropriately by determining balance constraints for each partitioning step and significantly improves the performance of cut- based placement, particularly timing perspective, as implemented within a state-of-the-art industrial placer.

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs

A novel design hierarchy identification technique to effectively identify design hierarchies and guide placement for better wirelength and routability and to further optimize routing congestion is presented.

GRPlacer: Improving routability and wire-length of global routing with circuit replacement

This study integrates global routing and placement to improve the wirelength estimation accuracy of placement and resolves the original congested regions of the placements generated by ROOSTER.



Dragon2000: standard-cell placement tool for large industry circuits

It is argued that net-cut minimization is a good and important shortcut to solve the large scale placement problem and is shown to be more important than greedily obtain a wirelength optimal placement at intermediate hierarchical levels.

Can recursive bisection alone produce routable, placements?

The state-of-the-art after two decades of research in recursive bisection placement is summarized and a new placer is implemented, called Capo, to empirically study the achievable limits of the approach and validates fixed-die placement results by violation-free detailed auto-routability.

Risa: Accurate And Efficient Placement Routability Modeling

An accurate and efficient placement routability modeling technique is proposed and incorporated into the prevailing simulated annealing approach based on the supply versus demand analysis of routing resource over an array of regions on a chip.

NRG: global and detailed placement

  • M. SarrafzadehMaogang Wang
  • Computer Science
    1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)
  • 1997
NRG, a new approach to the placement problem that consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular input, and shows that the output of the global placement can also serve as a fast and accurate predictor.

Congestion-driven placement using a new multi-partitioning heuristic

  • Stefan MayrhoferU. Lauther
  • Computer Science
    1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
  • 1990
A novel hierarchical top down placement technique is presented for circuits implemented in the sea-of-gates design style. It is based on a new hypergraph multi-partitioning algorithm, whose time

Congestion estimation during top-down placement

This is the first attempt to predict congestion using Rent's rule for early placement stages of VLSI physical design by combining the wirelength distribution model and inter-region wire estimation.

Estimating routing congestion using probabilistic analysis

A net-based stochastic model for computing expected horizontal and vertical track usage, which considers routing blockages is proposed, and the main advantages of this algorithm are accuracy and fast runtime.

A class of min-cut placement algorithms

A class of min-cut placement algorithms for solving some assignment problems related to the physical implementation of electrical circuits and the need for abandoning classical objective functions based upon distance, and introducing new objective functionsbased upon "signals cut".

GORDIAN: VLSI placement by quadratic programming and slicing optimization

The authors present a placement method for cell-based layout styles. It is composed of alternating and interacting global optimization and partitioning steps that are followed by an optimization of

Congestion reduction during placement based on integer programming

  • Xiaojian YangR. KastnerM. Sarrafzadeh
  • Computer Science, Business
    IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)
  • 2001
Experiments show that the proposed approach can effectively reduce the total overflow of global routing result and the short running time of the algorithm indicates good scalability on large designs.