Routability-driven placement and white space allocation

@inproceedings{Li2004RoutabilitydrivenPA,
  title={Routability-driven placement and white space allocation},
  author={Chen Li and Min Xie and Cheng-Kok Koh and Jason Cong and Patrick H. Madden},
  booktitle={ICCAD},
  year={2004}
}
We present a two-stage congestion-driven placement flow. First, during each refinement stage of our multilevel global placement framework, we replace cells based on the wirelength weighted by congestion level to reduce the routing demands of congested regions. Second, after the global placement stage, we allocate appropriate amounts of white space into different regions of the chip according to a congestion map by shifting cut lines in a top-down fashion and apply a detailed placer to legalize… Expand
Routability-driven placement and white space allocation
We present a congestion-driven placement flow. First, we consider in the global placement stage the routing demand to replace cells in order to avoid congested regions. Then we allocate appropriateExpand
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References

SHOWING 1-10 OF 47 REFERENCES
Routability driven white space allocation for fixed-die standard-cell placement
TLDR
A white space allocation approach that dynamically assigns white space according to the congestion distribution of the placement, combined with a multilevel placement flow, significantly improves placement routability and layout quality. Expand
Routability-driven placement and white space allocation
We present a congestion-driven placement flow. First, we consider in the global placement stage the routing demand to replace cells in order to avoid congested regions. Then we allocate appropriateExpand
Routability-driven placement and white space allocation
We present a congestion-driven placement flow. First, we consider in the global placement stage the routing demand to replace cells in order to avoid congested regions. Then we allocate appropriateExpand
An effective congestion driven placement framework
TLDR
A fast but reliable way to detect routing criticalities in VLSI chips by using a congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Expand
Can recursive bisection alone produce routable, placements?
TLDR
The state-of-the-art after two decades of research in recursive bisection placement is summarized and a new placer is implemented, called Capo, to empirically study the achievable limits of the approach and validates fixed-die placement results by violation-free detailed auto-routability. Expand
RISA: accurate and efficient placement routability modeling
TLDR
An accurate and efficient placement routability modeling technique is proposed and incorporated into the prevailing simulated annealing approach based on the supply versus demand analysis of routing resource over an array of regions on a chip. Expand
Effective free space management for cut-based placement via analytical constraint generation
TLDR
An enhancement to cut-based placement called analytic constraint generation (ACG), which utilizes an analytic engine to distribute available free space appropriately by determining balance constraints for each partitioning step and significantly improves the performance of cut- based placement, particularly timing perspective, as implemented within a state-of-the-art industrial placer. Expand
A robust detailed placement for mixed-size IC designs
  • J. Cong, M. Xie
  • Computer Science
  • Asia and South Pacific Conference on Design Automation, 2006.
  • 2006
TLDR
A three-step approach, named XDP, for mixed-size detailed placement, which is the only detailed placement that successfully produces legal placement for all the examples, while APlace and Fengshui fail for 4/9 and 1/3 of the examples. Expand
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
TLDR
A state-of-the-art recursive bisection placer is tuned to betterhandle regular netlists that offer a convenient way to represent memories, datapaths and random-logic IP blocks and better whitespace distribution improve results on recent mixed-size placement benchmarks. Expand
Multilevel global placement with congestion control
TLDR
A multilevel global placement algorithm (MGP) integrated with fast incremental global routing for directly updating and optimizing congestion cost during physical hierarchy generation and a hierarchical area density control is developed for placing objects with significant size variations. Expand
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