Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning

@article{Chan2017RoutabilityOF,
  title={Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning},
  author={Wei-Ting Jonas Chan and Pei-Hsin Ho and Andrew B. Kahng and Prashant Saxena},
  journal={Proceedings of the 2017 ACM on International Symposium on Physical Design},
  year={2017}
}
  • W. Chan, Pei-Hsin Ho, +1 author P. Saxena
  • Published 2017
  • Computer Science
  • Proceedings of the 2017 ACM on International Symposium on Physical Design
Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the placer to optimize the placement of the design to reduce detailed-route DRC violations. However, in sub-14nm processes and beyond, DRCs arising from multiple patterning and pin-access constraints drastically weaken the correlation between global-route… Expand
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