Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

@article{Tomizawa2011RobustSV,
  title={Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme},
  author={Hideyuki Tomizawa and S. T. Chen and Daniel Hor{\'a}k and Hayato Kato and Yunpeng Yin and Motoo Ishikawa and John Paul Kelly and C. S. Koay and Guillaume Landie and Sean D. Burns and Kazuyuki Tsumura and Masayoshi Tagami and Hosadurga Shobha and Muthumanickam Sankarapandian and O. van der Straten and Joseph S. Maniscalco and Tuan Anh Vo and J. C. Arnold and Matthew E. Colburn and Takamasa Nagoya-shi Usui and Terry A. Spooner},
  journal={2011 IEEE International Interconnect Technology Conference},
  year={2011},
  pages={1-3}
}
A self-aligned via(SAV) process was employed to build 64nm pitch Dual-Damascene(DD) interconnects using a pitch split double exposure pattering scheme to form the Cu lines. TiN hardmask (HM) density and thickness were optimized to achieve the SAV process and DD structure build. We present STEM cross sections of the structures after TiN HM deposition, HM open and DD RIE to determine the minimum required TiN HM thickness for the SAV process. We characterized the TiN loss for each RIE step from… CONTINUE READING

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