Robust SEU Mitigation of 32 nm Dual Redundant Flip-Flops Through Interleaving and Sensitive Node-Pair Spacing

  title={Robust SEU Mitigation of 32 nm Dual Redundant Flip-Flops Through Interleaving and Sensitive Node-Pair Spacing},
  author={M. Caba{\~n}as-Holmen and E. Cannon and Salim A. Rabaa and T. Amort and J. Ballast and Michael Carson and Duncan Lam and R. Brees},
  journal={IEEE Transactions on Nuclear Science},
We introduce the 32 nm SOI Boeing Interleaved Flip-Flop, which is based on the DICE topology with additional RHBD layout enhancements. Sensitive node pairs were separated by interleaving elements of the flip-flop cell, to attain the required SEU performance while minimizing the area, speed and power impact. The Boeing Interleaved Flip-Flop takes advantage of the reduced charge sharing inherent to an SOI technology to maintain a two order of magnitude SEU improvement relative to the unhardened… Expand
A Layout-Based Rad-Hard DICE Flip-Flop Design
This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the layout level, an alternative to existing Layout Design through Error-Aware Transistor Positioning (LEAP) and re-places transistors in master and slave DICE latches in the zigzag fashion in the layout. Expand
SEU and SET of 65 Bulk CMOS Flip-flops and Their Implications for RHBD
Two 65 nm bulk CMOS test chips, each containing several different types of flip-flop chains, are designed and tested. Heavy ion results are given and analyzed across ion LET and in proposed timeExpand
Multiple Layout-Hardening Comparison of SEU-Mitigated Filp-Flops in 22-nm UTBB FD-SOI Technology
The standard and layout-hardened D filp-flops (DFFs) named DFF1–6 were designed and manufactured based on an advanced 22-nm ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBBExpand
Utilizing Devi Hardene
  • 2014
Utilizing device stacking for area efficient hardened SOI flip-flop designs
D-flip-flop designs hardened with stacked transistors for a 32-nm SOI CMOS technology show greater than three orders of magnitude decrease in soft error cross-section, up to a heavy-ion tested tiltExpand
An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology
In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are introduced in the stackedExpand
The orientational dependence of single event upsets and multiple-cell upsets in 65 nm dual DICE SRAM
The impact of different orientational angle of ion incidence on SEU and MCU are studied in dual DICE SRAM according to directionality of different sensitive pairs. The results show the worstExpand
Porting & Scaling Strategies for Nanoscale CMOS RHBD
Techniques are described for minimizing the number of cells in a digital logic library, scaling and porting the cells to process nodes that do not nominally support scaling, and increasing theExpand
Porting and Scaling Strategies for Nanoscale CMOS RHBD
  • R. Shuler
  • Engineering, Computer Science
  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2015
A new compact modular 10T compact continuously-voting latch cell reduces circuitry to conventional latch sizes, at less power, allowing modular redundancy to approach theoretical efficiency limits. Expand
Low-Power Highly Reliable SET-Induced Dual-Node Upset-Hardened Latch and Flip-Flop
  • Riadul Islam
  • Computer Science
  • Canadian Journal of Electrical and Computer Engineering
  • 2019
The first SEDU-hardened flip-flop that exhibits negative hold time is presented and is proposed, which is 29% faster, consumes 50% lower dynamic power and 25% lower static power, has 45% lower setup time, and uses 27% lower area than the existing partial SEDUs. Expand


Area-Efficient Temporally Hardened by Design Flip-Flop Circuits
Two temporally hardened master-slave flip-flops are presented. Both designs utilize master latches containing Muller C-elements and dual redundant temporal hardening, as well as spatially interleavedExpand
An Area and Power Efficient Radiation Hardened by Design Flip-Flop
A radiation hardened by design flip-flop with high single event effect immunity is described. Circuit size and power are reduced by a combination of proven SEE hard techniques, i.e., a temporal latchExpand
Technology Scaling Comparison of Flip-Flop Heavy-Ion Single-Event Upset Cross Sections
Heavy-ion experimental results from flip-flops in 180-nm to 28-nm bulk technologies are used to quantify single-event upset trends. The results show that as technologies scale, D flip-flopExpand
Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process
Mitigation techniques to reduce the increased SEU cross-section associated with charge sharing in a 90 nm DICE latch are proposed. The increased error cross-section is caused by heavy ion angularExpand
Temporal sequential logic hardening by design with a low power delay element
A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient (SET) tolerance is demonstrated by simulations using itExpand
Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology
Alpha, neutron, and heavy-ion single-event measurements were performed on both high-performance and hardened flip-flop designs in a 28-nm bulk CMOS technology. The experimental results agree veryExpand
At-Speed SEE Testing of RHBD Embedded SRAMs
We describe a test structure architecture that allows at-speed Single Event Effects (SEE) testing on embedded memory arrays. The at-speed test structure enables identification of Multiple Cell UpsetsExpand
Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node
Neutron- and proton-induced single-event upset cross sections of D- and DICE-Flip/Flops are analyzed for designs implemented in a 40 nm bulk technology node. Neutron and proton testing of theExpand
Upset hardened memory design for submicron CMOS technology
A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs andExpand
Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction
Physical mechanisms of single-event effects that result in multiple-node charge collection or charge sharing are reviewed and summarized. A historical overview of observed circuit responses is givenExpand