Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols

@inproceedings{Chelcea2001RobustIF,
  title={Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols},
  author={Tiberiu Chelcea and Steven M. Nowick},
  booktitle={DAC},
  year={2001}
}
This paper presents several low-latency mixed-timing FIFO designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The design are then adapted to work between systems with very long interconnection delays, by migrating a single-clock solution by Carloni et al. (for “latency-insensitive” protocols) to mixed-timing domains. The new designs can be made arbitrarily robust with regard to metastability and interface… CONTINUE READING
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Fully Asynchronous Interface with Programmable Metastability Settling Time Synchronizer

  • J. Jex, C. Dike, K. Self
  • Patent No. 5,598,113
  • 1997
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