Rijndael FPGA implementation utilizing look-up tables

@article{McLoone2001RijndaelFI,
  title={Rijndael FPGA implementation utilizing look-up tables},
  author={W. McLoone and John V. McCanny},
  journal={2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)},
  year={2001},
  pages={349-360}
}
  • W. McLoone, J. McCanny
  • Published 26 September 2001
  • Computer Science
  • 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)
An FPGA Rijndael encryption design is presented, which utilizes look-up tables to implement the entire Rijndael Round function. A comparison is provided between this design and similar existing implementations. Hardware implementations of encryption algorithms prove much faster than equivalent software implementations and since there is a need to perform encryption on data in real time, speed is very important. In particular, field programmable gate arrays (FPGAs) are well suited to encryption… 

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References

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High performance single-chip FPGA implementations of the new Advanced Encryption Standard (AES) algorithm, Rijndael are described, with a novel, generic, parameterisable RIJndael encryptor core capable of supporting varying key sizes.
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