High performance computing systems consist of many modules of high complexity. To design such systems, the common bus architecture as interconnect poses a serious problem in terms of latency and throughput. To overcome the disadvantages of the common bus architecture, a new paradigm in ASIC design called the Network on Chip (NoC) was proposed[1,4,6]. Several topologies like 2D mesh, torus are used to interconnect the different modules using this novel idea. These topologies under performed when scaled. This paper proposes a new architecture RiCoBiT: RingConnected Binary Tree. It is a structured scalable architecture for the Network on Chip based systems. An optimal routing algorithm for it has been designed. The paper also studies the different properties and analyses parameters like maximum hop count, average hop count, latency, throughput bounds, number of wire segments and wirelength used to interconnect the nodes of RiCoBiT. These parameters are compared with that of 2D mesh and torus. It is found that RiCoBiT scales better.