Corpus ID: 39195871

Review on Floating Point Multiplier Using Vedic Mathematics

  title={Review on Floating Point Multiplier Using Vedic Mathematics},
  author={Snehal M. Khobragade and Mayur S. Dhait},
The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using ancient Vedic mathematics is presented. The… Expand

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