Corpus ID: 39195871

Review on Floating Point Multiplier Using Vedic Mathematics

@inproceedings{Khobragade2015ReviewOF,
  title={Review on Floating Point Multiplier Using Vedic Mathematics},
  author={Snehal M. Khobragade and Mayur S. Dhait},
  year={2015}
}
The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using ancient Vedic mathematics is presented. The… Expand

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References

SHOWING 1-10 OF 12 REFERENCES
A parallel IEEE P754 decimal floating-point multiplier
Small area reconfigurable FFT design by Vedic Mathematics
Design and implementation of floating point multiplier based on Vedic Multiplication Technique
  • A. Kanhe, S. Das, A. K. Singh
  • Computer Science
  • 2012 International Conference on Communication, Information & Computing Technology (ICCICT)
  • 2012
Comparison of IEEE754 Standard Single Precision Floating Point Multiplier ’ s
  • International Journal of Emerging Trends in Electrical and Electronics ( IJETEE )
  • 2013
Vedic Mathematics Sixteen Simple Mathematical Formulae from the Veda
  • 1965
Fine particles , thin films and exchange anisotropy
  • Magnetism
  • 1963
Khare,”Comparison of pipelined IEEE-754 standard floating point multiplier with unpipelined multiplier “Journal
  • in Magnetism,
  • 1963
...
1
2
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