Review on Design Approach for FPGA Implementation of 16-Bit Vedic Multiplier
@article{Moon2017ReviewOD, title={Review on Design Approach for FPGA Implementation of 16-Bit Vedic Multiplier}, author={S S Moon and Shailesh M. Sakhare}, journal={International Journal of Scientific Research in Science and Technology}, year={2017}, volume={3}, pages={191-195} }
In this paper, a high speed and low power 16x16 Vedic Multiplier is designed by using low power and high speed modified carry select adder. Modified Carry Select Adder employs a newly incremented circuit in the intermediate stages of the Carry Select Adder (CSA) which is known to be the fastest adder among the conventional adder structures. A Novel technique for digit multiplication namely Vedic multiplication has been introduced which is quite different from normal multiplication by shift and… CONTINUE READING
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