Reverse engineering of real PCB level design using VERILOG HDL

@inproceedings{Koutsougeras2002ReverseEO,
  title={Reverse engineering of real PCB level design using VERILOG HDL},
  author={Cris Koutsougeras and Nikolaos Bourbakis and Victor J. Gallardo},
  year={2002}
}
The repair or replacement of components nearing obsolescence and the lack of accuracy in technical information is a very common problem. Updating these systems is possible now with sophisticated CAE tools and the Hardware Description Languages. Here we consider the conversion process of a real board design from TTL implementation to newer technology. This process is performed through an Automatic Verilog HDL Model Generator, which includes an image analysis system, for component identification… CONTINUE READING

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