Reusing an on-chip network for the test of core-based systems

  title={Reusing an on-chip network for the test of core-based systems},
  author={{\'E}rika F. Cota and Luigi Carro and Marcelo Lubaszewski},
  journal={ACM Trans. Design Autom. Electr. Syst.},
Networks-on-chip are likely to become the main communication platform of systems-on-chip. To cope with the growing complexity of the test of such systems, the authors propose the reuse of the on-chip network as a test access mechanism to the cores embedded into systems that use this communication platform. An algorithm exploiting the network characteristics to minimize test time is presented. Then, the reuse strategy is evaluated considering a number of system configurations, such as different… CONTINUE READING
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