Reusable On-Chip System Level Verification for Simulation Emulation and Silicon

Abstract

Absolute verification of system on chip (SoC) has become infeasible due to the huge number of chip-level scenarios to cover. System level verification validates the integration of independently-verified components such as cores, peripherals, caches and memories. Some of the most elusive system level bugs can only be detected by scenarios that exercise… (More)
DOI: 10.1109/HLDVT.2006.319974
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