Retiming for High Performance FPGAs Considering Flip-flop Constraints and Process Variations

Abstract

Retiming is effective to improve performance of sequential circuits. The existing FPGA retiming techniques implicitly assume that an LUT can only drive a flip-flop (FF) within the same logic cell (LC). Leveraging all FFs within a same CLB, we propose an efficient FF constraint driven retiming algorithm (CDR), and further extend to statistical retiming (sCDR… (More)

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