Retiming With Non-zero Clock Skew, Variable Register, and Interconnect Delay

@article{Soyata1994RetimingWN,
  title={Retiming With Non-zero Clock Skew, Variable Register, and Interconnect Delay},
  author={Tolga Soyata and Eby G. Friedman},
  journal={IEEE/ACM International Conference on Computer-Aided Design},
  year={1994},
  pages={234-241}
}
A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delay. These delay components are incorporated into retiming by assigning Register Electrical Characteristics (RECs) to each edge in the graph representation of the synchronous circuit. A matrix (called the Sequential Adjacency Matrix or SAM) is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned… CONTINUE READING

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