Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation

@inproceedings{Kaivola2009ReplacingTW,
  title={Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation},
  author={Roope Kaivola and Rajnish Ghughal and Naren Narasimhan and Amber Telfer and Jesse Whittemore and Sudhindra Pandav and Anna Slobodov{\'a} and Christopher Taylor and Vladimir A. Frolov and Erik Reeber and Armaghan Naik},
  booktitle={CAV},
  year={2009}
}
Formal verification of arithmetic datapaths has been part of the estab- lished methodology for most Intel processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel Core TM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic… CONTINUE READING
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References

Publications referenced by this paper.
SHOWING 1-10 OF 21 REFERENCES

Formal Verification of Hardware Support for Advanced Encryption Standard

  • 2008 Formal Methods in Computer-Aided Design
  • 2008
VIEW 1 EXCERPT

Pre-RTL formal verification: An Intel experience

  • 2008 45th ACM/IEEE Design Automation Conference
  • 2008
VIEW 1 EXCERPT

Formal verification of high-level conformance with symbolic simulation

  • Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.
  • 2005
VIEW 1 EXCERPT

Using a reflective functional language for hardware verification and theorem proving

J. O’Leary
  • Third Workshop on Applied Semantics (APPSEM 2005), September 12–15, 2005, pp. 12–15
  • 2005
VIEW 2 EXCERPTS

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