Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost

@article{Kuo2008ReliabilityTF,
  title={Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost},
  author={T. Y. Kuo and Shu-Ming Chang and Ying-Ching Shih and C. W. Chiang and Chao-Kai Hsu and Ching Kuan Lee and Chun-Te Lin and Yu-Hua Chen and Wei-Chung Lo},
  journal={2008 58th Electronic Components and Technology Conference},
  year={2008},
  pages={853-858}
}
In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non… CONTINUE READING
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