Reliability in CMOS IC Design: Physical Failure Mechanisms and their Modeling

  • Published 2000

Abstract

There are a number of physical failure mechanisms that can affect the reliability of a CMOS ASIC. Some of the common mechanisms can be mitigated by adhering to foundry design rules (Electromigration, Time Dependent Dielectric Breakdown (TDDB), and Hot Carrier Damage). Certain fabrication steps can cause stress that may lead to latent damage that may later… (More)

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Cite this paper

@inproceedings{2000ReliabilityIC, title={Reliability in CMOS IC Design: Physical Failure Mechanisms and their Modeling}, author={}, year={2000} }