Reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories

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@article{Chang2015ReliabilityIO, title={Reliability impacts of high-speed 3-bit/cell Schottky barrier nanowire charge-trapping memories}, author={Wei Chang and Chun-Hsing Shih and Yan-Xiang Luo and Wen-Fa Wu and Chenhsin Lien}, journal={Microelectronics Reliability}, year={2015}, volume={55}, pages={74-80} }