Reliability characterization of Chip-on-Wafer-on-Substrate (CoWoS) 3D IC integration technology

@article{Lin2013ReliabilityCO,
  title={Reliability characterization of Chip-on-Wafer-on-Substrate (CoWoS) 3D IC integration technology},
  author={Larry Liang-Chen Lin and Tung-Chin Yeh and Jyun-lin Wu and G. C. Lu and T. J. Tsai and Larry Chen and An-Tai Xu},
  journal={2013 IEEE 63rd Electronic Components and Technology Conference},
  year={2013},
  pages={366-371}
}
With the size of transistors scaling down, 3D IC packaging emerged as one of the most promising solutions to achieve system integration on the track of Moore's Law. In this article, we demonstrated a sub-system with one 28nm logic device and two 40nm chips on a 600mm2 silicon interposer with Through-Silicon-Via (TSV) integrating 4 layers of high density… CONTINUE READING