Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring


The growing technology scaling and larger die size of multi-processor System-On-Chip have increased the error rates for on-chip memories. Increased system speed for high performance, aggressive voltages scaling for power reduction and intra-die process variation have exaggerated the unreliability issue. In this paper a method for memory management on SoCs… (More)
DOI: 10.1109/VLSID.2015.97


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