Improving Translation of Live Sequence Charts to Temporal Logic
Variants of sequence diagrams are used in UML-based development processes to capture “scenarios”, i.e. representative sequences of interactions between objects, to clarify use-cases of the system under design. A set of scenarios provides a starting point for a formal specification to be verified. The sequence diagram variant SD of UML lacks formal rigor and expressivity so we propose to use Live Sequence Charts instead. Since the semantics of Live Sequence Charts is defined in terms of abstract “instances”, the contribution of this work is to give an interpretation of LSCs with free variables. This is a single small step in an ongoing effort to establish a verification environment for UML models.