• Corpus ID: 13998559

Regular Paper Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis

@inproceedings{Hara2009RegularPP,
  title={Regular Paper Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis},
  author={Yuko Hara and Hiroyuki Tomiyama and Shinya Honda and Hiroaki Takada},
  year={2009}
}
In general, standard benchmark suites are critically important for researchers to quantitatively evaluate their new ideas and algorithms. This paper proposes CHStone, a suite of benchmark programs for C-based high-level synthesis. CHStone consists of a dozen of large, easy-to-use programs written in C, which are selected from various application domains. This paper also analyzes the characteristics of the CHStone benchmark programs, which will be valuable for researchers to use CHStone for the… 

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References

SHOWING 1-10 OF 10 REFERENCES
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
This paper proposes a behavioral level partitioning method for efficient behavioral synthesis from a large sequential program consisting of a set of functions. Our method optimally determines
MiBench: A free, commercially representative embedded benchmark suite
TLDR
A new version of SimpleScalar that has been adapted to the ARM instruction set is used to characterize the performance of the benchmarks using configurations similar to current and next generation embedded processors.
SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits
TLDR
This work Parallelizing High-Level Synthesis (PHLS) and its Methodology, which combines pre-Synthesis Compiler Optimizations, code Transformations and Scheduling, and Resource Binding and Control Synthesis, aims to bring high-level synthesis closer to reality.
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective
TLDR
This paper discusses the problems of the design productivity gap caused by the SoC's complexity and the timing closure caused by deep-submicrometer technology, and proposes a C-based SoC design environment that features integrated high-level synthesis (HLS) and verification tools.
MediaBench: a tool for evaluating and synthesizing multimedia and communications systems
TLDR
MediaBench is presented, a benchmark suite that has been designed to fill a gap between the compiler community and embedded applications developers and has been constructed through a three-step process: intuition and market driven initial selection, experimental measurement to establish uniqueness, and integration with system synthesis algorithms to establish usefulness.
High ― Level Synthesis: Introduction to Chip and System Design
TLDR
This paper presents a methodology for High-Level Synthesis of Architectural Models in Synthesis and its applications in Design Description Languages and Design Representation and Transformations.
PVRG-JPEG CODEC 1.1
TLDR
This package is based on the UNIX operating system and is dedicated to the standardization committees and their efforts in bringing the advancement of technology to everyone.
Hardware Synthesis from C/C++ Models
TLDR
Novel approaches have helped in reducing the semantic gap, and in easing the creation of design flows that support system-level specifications in C/C++.
SoftFloat (online). http://www.jhauser.us/arithmetic/SoftFloat.html (accessed 2009-07-07)
  • 2009
Benchmarks for the 1992 High Level Synthesis Workshop
  • Technical Report 92–107,
  • 1992