• Corpus ID: 15427862

Refreshing Thoughts on DRAM : Power Saving vs . Data Integrity

  title={Refreshing Thoughts on DRAM : Power Saving vs . Data Integrity},
  author={Amir Rahmati and Matthew Hicks and Daniel E. Holcomb and Kevin Fu},
To head-off the trend of increasing power consumption and throughput overheads due to refresh in DRAM, researchers are exploring ways to fine-tune refresh rate. Refresh management proposals range from temperature-aware refresh to partitioning data cells based on volatility, with each partition having its own refresh rate. One hurdle in this area is the lack of precise description of the evaluation setups used in current proposals. The incomplete description makes it difficult to reproduce… 

Figures and Tables from this paper

Sparkk : Quality-Scalable Approximate Storage in DRAM
This proposal is able to save more refresh power and enables a more effective storage of non-critical data by utilizing a non-uniform refresh of multiple DRAM chips and a permutation of the bits to theDRAM chips.
Quality Configurable Approximate DRAM
This paper proposes four novel strategies for partitioning the DRAM in a system into a number of quality bins based on the frequency, location, and nature of bit errors in each of the physical pages, while also taking into account the property of variable retention time exhibited by DRAM cells.
Memory-Aware Scheduling for Fixed Priority Hard Real-Time Computing Systems
This dissertation focuses on studying how to schedule high-priority hard real-time tasks with memory impacts taken into considerations, and develops an approach that takes into consideration the increasing transistor density and surging access demands from a rapidly growing number of processing cores.
Mitigating Wordline Crosstalk Using Adaptive Trees of Counters
A Counter-based Adaptive Tree (CAT) approach to mitigate wordline crosstalk using adaptive trees of counters to guide appropriate refreshing of vulnerable rows by tuning the distribution of the counters to the rows in a bank based on the memory reference patterns.
Processor/memory Co-Scheduling using periodic resource server for real-time systems under peak temperature constraints
The approach takes advantage of the periodic resource model for its hard deadline guarantee capability and in the meantime, by periodically (deterministically) throttling the accesses of the CPU and memory resources, can effectively guarantee the thermal constraints for both theCPU and memory.
Energy-efficient hardware design based on high-level synthesis
This dissertation describes research activities broadly concerning the area of High-level synthesis, but more specifically, regarding the HLS-based design of energy-efficient hardware (HW) accelerators and the development of a methodology complementing HLS to automatically derive power optimization directives.
Special Session: Reliability Analysis for ML/AI Hardware
The reliability issues in a commercial systolic array-based ML accelerator in the presence of faults engendering from devicelevel non-idealities in the DRAM are outlined and a system-level approach to mitigate them is presented.
Special Session: Reliability Analysis for AI/ML Hardware
The reliability issues in a commercial systolic array-based ML accelerator in the presence of faults engendering from device-level non-idealities in the DRAM are outlined and a system-level approach to mitigate them is presented.
Attacking and Defending Emerging Computer Systems Using The Memory Remanence Effect
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
A Platform to Analyze DDR3 DRAM’s Power and Retention Time
The authors explore the intrinsic trade-off in a DRAM between the power consumption (due to refresh) and the reliability and their unique platform allows tailoring to the design constraints depending on whether power consumption, performance or reliability has the highest design priority.


Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
An analysis of DDR4 DRAM's FGR feature is conducted, and there is no one-size-fits-all option across a variety of applications, and Adaptive Refresh is presented, a simple yet effective mechanism that dynamically chooses the best FGR mode for each application and phase within the application.
Flikker: saving DRAM refresh-power through critical data partitioning
Flikker exposes and leverages an interesting trade-off between energy consumption and hardware correctness, and shows that many applications are naturally tolerant to errors in the non-critical data, and in the vast majority of cases, the errors have little or no impact on the application's final outcome.
RAIDR: Retention-aware intelligent DRAM refresh
This paper proposes RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times and group DRAM rows into retention time bins and apply a different refresh rate to each bin.
RAMZzz: Rank-aware DRAM power management with dynamic migrations and demotions
This paper proposes a novel memory system design named RAMZzz with rank-aware energy saving optimizations that relies on a memory controller to monitor the memory access locality, and group the pages with similar access locality into the same rank.
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM
This work proposes retention-aware placement in DRAM (RAPID), novel software approaches that can exploit off-the-shelf DRAMs to reduce refresh power to vanishingly small levels approaching non-volatile memory.
Hardware/software techniques for DRAM thermal management
This work develops a thermal model to estimate the temperature of DRAM chips and proposes three hardware and software schemes to reduce peak temperatures, and introduces a new cache line replacement policy that reduces the number of accesses to the overheatingDRAM chips.
Memory power management via dynamic voltage/frequency scaling
A large opportunity for memory power reduction is demonstrated with a simple control algorithm that adjusts memory voltage and frequency based on memory bandwidth utilization, and a simple algorithm is evaluated in a real system.
On the retention time distribution of dynamic random access memory (DRAM)
The retention time distribution of high-density dynamic random access memory (DRAM) has been investigated. The key issue for controlling the retention time distribution has been clarified and its
An Analysis of Power Consumption in a Smartphone
A detailed analysis of the power consumption of a recent mobile phone, the Openmoko Neo Freerunner, measuring not only overall system power, but the exact breakdown of power consumption by the device's main hardware components.
Block-based multi-period refresh for energy efficient dynamic memory
  • Joohee KimM. Papaefthymiou
  • Computer Science
    Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)
  • 2001
A novel scheme that relies on multiple refresh periods and small refresh blocks to reduce DRAM dissipation by decreasing the number of cells refreshed too often and gives a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh.