Reduction of Current Mismatch in PLL Charge Pump

@article{Fazeel2009ReductionOC,
  title={Reduction of Current Mismatch in PLL Charge Pump},
  author={H. Md. Shuaeb Fazeel and Leneesh Raghavan and Chandrasekaran Srinivasaraman and Manish Jain},
  journal={2009 IEEE Computer Society Annual Symposium on VLSI},
  year={2009},
  pages={7-12}
}
Low static phase offset is desired in Phase Locked Loops (PLL) employed in high speed I/O interfaces and frequency synthesizers. In this work, non idealities in phase frequency detector and charge pump contributing to static phase offset have been studied and their relative contributions analyzed in detail. A new charge pump architecture with reduced mismatch between Up and Dn current sources has been presented. It makes use of a single two stage amplifier for both current steering and… CONTINUE READING

Citations

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High performance two-stage charge-pump for spur reduction in CMOS PLL

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