Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching

@inproceedings{Romanescu2008ReducingTI,
  title={Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching},
  author={Bogdan F. Romanescu and Michael E. Bauer and Sule Ozev and Daniel J. Sorin},
  booktitle={Conf. Computing Frontiers},
  year={2008}
}
We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components-including registers, functional units, and L1I and L1D cache frames-without slowing the clock frequency or pessimistically assuming that all components are slow. Using ideas previously developed for other purposes-criticality-based allocation of resources, prefetching, and prefetch buffering-we allow design engineers to aggressively set the clock… CONTINUE READING

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