Reducing the complexity of the register file in dynamic superscalar processors

  title={Reducing the complexity of the register file in dynamic superscalar processors},
  author={Rajeev Balasubramonian and Sandhya Dwarkadas and David H. Albonesi},
Dynamic superscalar processors execute multiple instructions out-of-order by looking for independent operations within a large window. The number of physical registers within the processor has a direct impact on the size of this window as most in-flight instructions require a new physical register at dispatch. A large multi-ported register file helps improve the instruction-level parallelism (ILP), but may have a detrimental effect on clock speed, especially in future wire-limited technologies… CONTINUE READING
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