Reducing test time via an optimal selection of LFSR feedback taps

Abstract

D The results of a simulation study demonstrate that in linear feedback shift register-based built-in VLSI testing, the selection of proper feedback taps can reduce the test application time while retaining the testability goals 
DOI: 10.1109/ISSPA.2001.949837

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Cite this paper

@inproceedings{Afaq2001ReducingTT, title={Reducing test time via an optimal selection of LFSR feedback taps}, author={Ahmad Afaq and Ali Al-Lawati}, booktitle={ISSPA}, year={2001} }