Reducing read latency of phase change memory via early read and Turbo Read

@article{Nair2015ReducingRL,
  title={Reducing read latency of phase change memory via early read and Turbo Read},
  author={Prashant Jayaprakash Nair and Chia-Chen Chou and Bipin Rajendran and Moinuddin K. Qureshi},
  journal={2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)},
  year={2015},
  pages={309-319}
}
Phase Change Memory (PCM) is an emerging memory technology that can enable scalable high-density main memory systems. Unfortunately, PCM has higher read latency than DRAM, resulting in lower system performance. This paper investigates architectural techniques to improve the read latency of PCM. We observe that there is a wide distribution in cell resistance in both the SET state and the RESET state, and that the read latency of PCM is designed conservatively to handle the worst case cell. If… CONTINUE READING
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SHOWING 1-10 OF 39 REFERENCES

Explanation of programming distributions in phase-change memory arrays based on crystallization time statistics

  • D. Mantegazza, D. Ielmini, +4 authors R. Bez
  • Solid-State Electronics, vol. 52, no. 4, pp. 584…
  • 2008
Highly Influential
4 Excerpts

A note on error detection codes for asymmetric channels

  • J. Berger
  • Information and Control, vol. 4, no. 1, pp. 68…
  • 1961
Highly Influential
6 Excerpts

Controlling program parameters to increase nand flash life for ssd applications

  • C. Race, Y. P. Kim, R. Bowman
  • NVMW, .
  • 2014
1 Excerpt

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