Reducing process variation impact on replica-timed static random access memory sense timing

Abstract

The read access delay of a static random access memory (SRAM) is dominated by the time required to develop a voltage differential on the bit-lines, particularly for small, fast level-1 (L1) caches in microprocessors. For a robust design, the bit-lines must develop a differential sufficient to overcome mismatch due to sense amplifier offsets and other signal… (More)
DOI: 10.1016/j.vlsi.2009.03.002

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Cite this paper

@article{Desai2009ReducingPV, title={Reducing process variation impact on replica-timed static random access memory sense timing}, author={Nishith N. Desai and Jonathan R. Haigh and Lawrence T. Clark}, journal={Integration}, year={2009}, volume={42}, pages={437-448} }