Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

Modern microprocessors employ one or two levels of on-chip caches to bridge the burgeoning speed disparities between the processor and the RAM. These SRAM caches are a major source of power dissipation. We investigate architectural techniques, that do not compromise the processor cycle time, for reducing the power dissipation within the on-chip cache… CONTINUE READING

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