Reducing misses to external memory accesses in task-level pipelining


Recently, researchers have shown an increased interest in using task-level pipelining to accelerate the overall execution of applications mainly consisting of producer-consumer tasks. This paper proposes optimization techniques for enhancing our approach to pipeline the execution of producer-consumer tasks in FPGA-based multicore architectures with… (More)
DOI: 10.1109/ISCAS.2015.7168910


9 Figures and Tables

Cite this paper

@article{Azarian2015ReducingMT, title={Reducing misses to external memory accesses in task-level pipelining}, author={Ali Azarian and Jo{\~a}o M. P. Cardoso}, journal={2015 IEEE International Symposium on Circuits and Systems (ISCAS)}, year={2015}, pages={1422-1425} }