Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture

@inproceedings{Sharifi2003ReducingTP,
  title={Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture},
  author={Shervin Sharifi and Mohammad Hosseinabady and Pedram A. Riahi and Zainalabedin Navabi},
  booktitle={DFT},
  year={2003}
}
Time, power and data volume are among the most challenging problems in test of System-onChip (SoC) devices. These problems become even more important in scan-based test. The Selective Trigger Scan architecture introduced in this paper addresses these problems. This architecture reduces switching activity in circuit-under-test (CUT) and increases the scan clock frequency. Format of data for this reduced activity architecture enables us to perform a good compression and further reduce the test… CONTINUE READING