Reducing DRAM Latencies with an Integrated Memory Hierarchy Design

@inproceedings{Lin2001ReducingDL,
  title={Reducing DRAM Latencies with an Integrated Memory Hierarchy Design},
  author={Wei-Fen Lin and Steven K. Reinhardt and Doug Burger},
  booktitle={HPCA},
  year={2001}
}
In this paper, we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory system using four Direct Rambus channels and an integrated one-megabyte level-two cache, a processor still spends over half of its time stalling for L2 misses. Large cache blocks can improve performance, but only when coupled with wide memory channels. DRAM address mappings also affect performance significantly. We… CONTINUE READING
Highly Influential
This paper has highly influenced 19 other papers. REVIEW HIGHLY INFLUENTIAL CITATIONS
Highly Cited
This paper has 240 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 156 extracted citations

241 Citations

0102030'01'04'08'12'16
Citations per Year
Semantic Scholar estimates that this publication has 241 citations based on the available data.

See our FAQ for additional information.

Similar Papers

Loading similar papers…