Reducing DRAM Latencies with an Integrated Memory Hierarchy Design

  title={Reducing DRAM Latencies with an Integrated Memory Hierarchy Design},
  author={Wei-Fen Lin and Steven K. Reinhardt and Doug Burger},
In this paper, we address the severe performance gap caused by high processor clock rates and slow DRAM accesses. We show that even with an aggressive, next-generation memory system using four Direct Rambus channels and an integrated one-megabyte level-two cache, a processor still spends over half of its time stalling for L2 misses. Large cache blocks can improve performance, but only when coupled with wide memory channels. DRAM address mappings also affect performance significantly. We… CONTINUE READING
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