Reduced n<sup>+</sup>/p<sup>+</sup>-spacing with high latchup hardness in self-aligned double well CMOS technology

Abstract

Latchup in CMOS circuit with an epitaxial layer originates from short channel effects of the parasitic field oxide transistors and from voltage drops on shunt resistances. The short channel behaviour of the field oxide transistors was improved by reducing the p-well depth and modifying the local oxidation step for the well generation. By laser scanning… (More)

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4 Figures and Tables