Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM-based FPGAs

  • Vikram Chandrasekhar Sk Noor
  • Published 2005

Abstract

This paper proposes an efficient alternative to Triple Modular Redundancy for SEU mitigation in SRAM-based FPGAs. The new technique, Reduced Triple Modular Redundancy (RTMR), operates on a lookup-table (LUT) network obtained after the technology mapping stage. The entire set of LUTs is classified on the basis of sensitivity into sensitive, internally… (More)

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