Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications

Abstract

Low-latency Network-on-Chip (NoC) applications have tight constraints on the clock budget to perform communication among nodes. This is a critical aspect in NoC-based designs where the number of clock cycles spent for communication depends mainly on the topology and on the routing algorithm. This work deals with logarithmic diameter topologies, that were… (More)
DOI: 10.1109/PDP.2014.85

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