Reconfigurable Silicon Photonic Interconnect for Many-Core Architecture

@inproceedings{Guan2017ReconfigurableSP,
  title={Reconfigurable Silicon Photonic Interconnect for Many-Core Architecture},
  author={Hang Guan and S{\'e}bastien Rumley and Ke Wen and David Donofrio and John Shalf and Keren Bergman},
  booktitle={ISC Workshops},
  year={2017}
}
In the context of declining Moore and Dennard Laws, efficient utilization of chip area and transistor is more than ever required. The portion of transistors devoted to compute operations can be maximized by off-loading as much as possible data-storage onto memory chips. This, however, requires wide off-chip IO bandwidth, and furthermore increases Network-on-chip (NoC) traffic. In this paper, we first present a concept of optically connected memory modules, delivering enough bandwidth to allow… 

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References

SHOWING 1-10 OF 17 REFERENCES

Silicon photonic memory interconnect for many-core architectures

TLDR
This paper proposes a reconfigurable Silicon photonic memory interconnect based on 2.5D stacking that can direct memory traffic to any memory interface on the processor, thus alleviating the two important issues of many-core memory accesses: traffic hotspots and non-uniform memory access (NUMA).

Re-architecting DRAM memory systems with monolithically integrated silicon photonics

TLDR
This work redesigns the DRAM main memory system using a proposed monolithically integrated silicon photonics technology and shows that the photonically interconnected DRAM (PIDRAM) provides a promising solution to all of these issues.

Energy-performance optimized design of silicon photonic interconnection networks for high-performance computing

TLDR
Detailed electrical and optical models of the elements that comprise a WDM silicon photonic link are presented to analyze the energy consumption and scalability of the link by finding the right combination of channels × data rate per channel that fully covers the available optical power budget.

Single-chip microprocessor that communicates directly using light

TLDR
This demonstration could represent the beginning of an era of chip-scale electronic–photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Silicon photonics for next generation system integration platform

TLDR
It is shown that an optical interposer is the most efficient way to cope with the various problems that a purely electronic system may encounter and will solve those interconnection problems.

Comprehensive Design Space Exploration of Silicon Photonic Interconnects

The paper presents a comprehensive physical layer design and modeling platform for silicon photonic interconnects. The platform is based on explicit closed-form expressions for optical power

A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS

TLDR
This work demonstrates a silicon-photonic link with optical devices and electronics integrated on the same chip in a 0.18 μm bulk CMOS memory periphery process, and introduces deep-trench isolation, placed underneath to prevent optical mode leakage into the bulk silicon substrate, and implant-amorphization to reduce polysilicon loss.

Flexfly: Enabling a Reconfigurable Dragonfly through Silicon Photonics

  • Ke WenP. Samadi Jeremiah J. Wilke
  • Computer Science
    SC16: International Conference for High Performance Computing, Networking, Storage and Analysis
  • 2016
TLDR
This work built a 32-node Flexfly prototype using a Silicon photonic switch connecting four groups and demonstrated 820 ns interconnect reconfiguration time, which is up to 1.8× speedup over Dragonfly paired with UGAL routing, along with halved hop count and latency for cross-group messages.

Integration of silicon photonics into electronic processes

TLDR
An overview of required process features, device design guidelines and integration methodology tradeoffs, as well as achievable photonic device performance will be presented within the context of monolithic front-end integration within state-ofthe- art electronics processes.

Silicon Photonic Circuits: On-CMOS Integration, Fiber Optical Coupling, and Packaging

TLDR
Recent progress in the packaging of silicon photonic circuits from on-CMOS wafer-level integration to the single-chip package and input/output interconnects is reviewed, focusing on optical fiber-coupling structures comparing edge and surface couplers.