Reconfigurable Silicon Photonic Interconnect for Many-Core Architecture

  title={Reconfigurable Silicon Photonic Interconnect for Many-Core Architecture},
  author={Hang Guan and S{\'e}bastien Rumley and Ke Wen and David Donofrio and John Shalf and Keren Bergman},
  booktitle={ISC Workshops},
In the context of declining Moore and Dennard Laws, efficient utilization of chip area and transistor is more than ever required. The portion of transistors devoted to compute operations can be maximized by off-loading as much as possible data-storage onto memory chips. This, however, requires wide off-chip IO bandwidth, and furthermore increases Network-on-chip (NoC) traffic. In this paper, we first present a concept of optically connected memory modules, delivering enough bandwidth to allow… 

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Flexfly: Enabling a Reconfigurable Dragonfly through Silicon Photonics

  • Ke WenP. Samadi Jeremiah J. Wilke
  • Computer Science
    SC16: International Conference for High Performance Computing, Networking, Storage and Analysis
  • 2016
This work built a 32-node Flexfly prototype using a Silicon photonic switch connecting four groups and demonstrated 820 ns interconnect reconfiguration time, which is up to 1.8× speedup over Dragonfly paired with UGAL routing, along with halved hop count and latency for cross-group messages.

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An overview of required process features, device design guidelines and integration methodology tradeoffs, as well as achievable photonic device performance will be presented within the context of monolithic front-end integration within state-ofthe- art electronics processes.

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