Reconfigurable Computing Based on Universal Configurable Blocks-A New Approach for Supporting Performance- and Realtime-Dominated Applications

Abstract

A novel architecture for reconfigurable computing based on a coarse grain FPGA-like architecture is introduced. The basic blocks contain all arithmetical and logical capacities as well as some registers and will be programmable by sequential instruction streams produced by software compiler. Reconfiguration is related to hyperblocks of instructions. For the composed reconfigurable processors a classification is introduced for describing realtime, multithreading and performance capabilities. 1. Motivation of the Approach Since the introduction of the von-Neuman-model of processors, scientists all over the world were looking for methods of parallelizing the execution of sequential programs resulting in many architectures and algorithms. With upcoming field-programmable hardware (FPL), first available in 1977 and since 1985 capable of integrating complete systems on one chip, a new programming paradigm was introduced now called structural programming. The difference between both programming paradigms results directly from basic architecture models: Controlflow based (von-Neuman) versus data-flow based (structurable hardware). Until now, no common execution model for both paradigms has been presented. Even the connection between microprocessor and field-programmable hardware seems to be much more improvable [1]. The most important advantage of one unified (hardware) model for sequential as well as structural programming could be the runtime variability of executing program units. The software designer or even the operating system could decide how to ‘execute’ any part in a more software (sequential) or hardware (structural) manner. In the authors’ opinion the missing common model and connectivity are the most important reasons for all difficulties of introducing Hardware/Software Co-Design methods on a broad base. Despite that applications with great advances in speed-up through co-design are innumerable, there exists any general model – with exceptions. A good overview for co-design methodologies and related topics is presented in [2] [3]. The most important exception are the F-CCMs, which means the class of Customized Computing Machines based on Field Programmable Gate Arrays. For subclasses of the F-CCMs, e.g. the PDD-CCMs (Procedurally Data Driven, [2]), models are presented with the result of successful introduction of automatic methods. The success of these PDD-CCMs, e.g. the Xputer [4], makes it worth to research for a more global model for ’executing programs‘ (in whatever context this is interpreted). This is the goal of the paper: to present a (partial) unified execution model. The model is based on the architecture of the Universal Configurable Blocks (UCB) in connection with the Procedural Driven Structural Programming algorithm (PDSP), which translates a flow of (non-control-)instructions into the UCB structure. The remainder of this paper will introduce and briefly discuss the UCB architecture (section 2) and the PDSP algorithm (section 3). Universal Configurable Machines (UCM) will be introduced in section 4. This is a new class of programmable machines using UCB for block based computations, and as these processor-like machines represent a non-classical approach, a classification system for UCMs is introduced. Section 5 scratches the software side of the reconfigurable architecture by a short view on the design methodologies and the impacts on the operating system. The use of blocks for the execution of programs and the availability of a multi-block machine enables the designer to manually decide between program-sequential and exclusive execution. This kind of hardware/software co-design will be also discussed. The paper finishes with a conclusion, an outlook to future work and some references. 2. Universal Configurable Blocks (UCB) A Universal Configurable Block (UCB) (see Figure 1) consists of a register file, a configurable asynchronous network with some arithmetical and logical capacity and optionally some auxiliary circuits. Optionally a load/store pipeline as well as private memory (random access or stack organised) may be added to the UCB. The width of data busses and registers inside is related to the actual implementation and may vary between different instantiations. Arithmet ical Unit (Type A)

DOI: 10.1109/ACAC.2000.824328

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Cite this paper

@inproceedings{Siemers2000ReconfigurableCB, title={Reconfigurable Computing Based on Universal Configurable Blocks-A New Approach for Supporting Performance- and Realtime-Dominated Applications}, author={Christian Siemers and Sybille Siemers}, booktitle={ACAC}, year={2000} }