Reclocking for high-level synthesis

  title={Reclocking for high-level synthesis},
  author={Pradip K. Jha and Nikil D. Dutt and Sri Parameswaran},
| In this paper we describe, a powerful post{synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire delays of designs created by a high level synthesis system, and then nding an optimal clockwidth, we resynthesize the controller to improve performance without altering the datapath. Reclocking is versatile and can be applied not only for wire delay consideration, but also for bit{width migration, library migration and… CONTINUE READING