Recent progress in synthesis for testability


Describes recent work involving the automatic synthesis of VLSI circuits with testability considerations. The first put of this paper explores the potential for logic synthesis to allow designers to more comprehensively test circuits while simultaneously diminishing the need for fault simulation and automatic test pattern generation. Logic optimization… (More)
DOI: 10.1109/VTEST.1991.208127


Figures and Tables

Sorry, we couldn't extract any figures or tables for this paper.

Slides referencing similar topics