Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture

@article{Morano2003RealizingHI,
  title={Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture},
  author={David Morano and Alireza Khalafi and David R. Kaeli and Augustus K. Uht},
  journal={SIGARCH Computer Architecture News},
  year={2003},
  volume={31},
  pages={16-25}
}
A microarchitecture is described that achieves high performance on conventional single-threaded program codes without compiler assistance. To obtain high instructions per clock (IPC) for inherently sequential (e.g., SpecInt-2000 programs), a large number of instructions must be in flight simultaneously. However, several problems are associated with such microarchitectures, including scalability, issues related to control flow, and memory latency.Our design investigates how to utilize a large… CONTINUE READING