Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers

@article{Arkin2004RealizingAP,
  title={Realizing a production ATE custom processor and timing IC containing 400 independent low-power and high-linearity timing verniers},
  author={Brian Arkin},
  journal={2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)},
  year={2004},
  pages={348-349 Vol.1}
}
An ATE processor and timing IC that includes 400 low-power timing verniers with a linearity error of less than 35ps is described. The timing vernier design approach is presented in detail. This 16x16mm/sup 2/ 62M transistor IC is implemented in foundry portable 0.18/spl mu/m CMOS technology. 

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