Realization of vertical resistive memory (VRRAM) using cost effective 3D process

  title={Realization of vertical resistive memory (VRRAM) using cost effective 3D process},
  author={I. G. Baek and Chan Jun Park and Hyunsu Ju and Dong-jun Seong and H. S. Ahn and J H Kim and Min Kyu Yang and Seung-hwan Song and Eun Mi Kim and S. O. Park and Chul Hong Park and C Wenyu Song and G. T. Jeong and Siyoung Q Choi and H. K. Kang and C. Chung},
  journal={2011 International Electron Devices Meeting},
Vertical ReRAM (VRRAM) has been realized with modification of Vertical NAND (VNAND) process and architecture as a cost-effective and extensible technology for future mass data storage. Dedicated ALD/CVD deposition and wet etching processes were developed to reproduce planar ReRAM properties in VRRAM structure. Multi-stack of VRRAM cell layers were fabricated at the same time using ALD TaOx/barrier layer/CVD TiN cell stacks. Oxidation control without intermixing has been found very critical in… CONTINUE READING
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