Realization of Gmicro/200

@article{Inayoshi1988RealizationOG,
  title={Realization of Gmicro/200},
  author={H. Inayoshi and Ikuya Kawasaki and Tadahiko Nishimukai and Ken Sakamura},
  journal={IEEE Micro},
  year={1988},
  volume={8},
  pages={12-21}
}
The Gmicro/200, a microprocessor that has been developed as part of Japan's TRON (The Real-Time Operating Nucleus) project, is described. This microprogram-based processor with six-state pipeline, 730000 transistors and on-chip caches will serve in an engineering workstation or a high-speed graphics accelerator system. The authors discuss features of the instruction set; memory management; handling of exceptions, interrupts and traps; and the implementation of the Gmicro/200.<<ETX>> 
The Gmicro/500 superscalar microprocessor with branch buffers
The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented.
The Gmicro/100 32-bit microprocessor
TLDR
The prejump mechanism, implemented as a hardware solution for the jump problem, executes benchmark programs 16.8% faster on the average and Optimized microinstructions permit bitmap-manipulation instructions to perform two to five times faster than the software loops.
GMICRO/500 microprocessor application system: Performance evaluation of graphic primitives
The GMICRO/500 is a high-performance 32-b microprocessor based on TRON specification. It operates at 66-MHz and achieves a processing rate of 130 MIPS. Its application system was developed to
32-bit microprocessors based on the TRON specification
TLDR
An introduction to the chip architecture of the TRON specification for the 32-bit general-purpose microprocessor and its relations with operating systems designed in other TRON subprojects are discussed.
GMICRO/500 microprocessor: pipeline structure of superscalar architecture
The GMICRO/500 pipelined instruction execution mechanism is described. The 5-stage dual-pipeline superscalar architecture is examined and examples of basic instruction execution timing are analyzed,
Recent advances in TRON-spec. chips
  • O. Tomisawa
  • Computer Science
    Proceedings Eighth TRON Project Symposium
  • 1991
TLDR
Operating systems based on the BTRON and ITRON specifications now run on these chips, which revealed superiority of the TRON instruction set architecture.
Performance evaluation of GMICRO/500 microprocessor for CTRON based kernel
TLDR
An evaluation system for the CTRON based kernel interface is developed to evaluate the execution time of each system call under the several conditions of the GMICRO/500 microprocessor.
Architectural features of OKI 32-bit microprocessor
TLDR
A 32-bit microprocessor to be used as a processor for a communication network node or engineering work station is being developed, and various techniques, such as six-stage pipelining, two internal caches for instruction codes and operand data, and full-associative address translation look-aside buffer, have been integrated.
A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming
A description is given of the Gmicro/FPU (floating-point unit), a chip that provides floating-point instructions for both the Gmicro/200 and the Gmicro/300 microprocessors. The VLSI
The approach to multiple instruction execution in the GMICRO/400 processor
TLDR
This paper describes the instruction execution mechanism of the 32-bit microprocessor GMICRO/400 that executes more than one operation per clock cycle and utilizes both superscalar and VLIW design techniques.
...
1
2
...

References

SHOWING 1-4 OF 4 REFERENCES
Architecture of the TRON VLSI CPU
TLDR
The TRON microprocessor has an open architecture, it will be expandable to 64-bit operations, and its design reflects the needs of a family of application-specific operating system kernels.
Benchmarks Contrast 68020 CacheMemory Operations,
  • EDN, Aug
  • 1985
A Tale of Four pPs: Benchmarks Quantity Performance,
  • EDN, Apr
  • 1981