Realistic analysis of limited parallel software/hardware implementations

Abstract

Proposed real-time system implementations combine reconfigurable hardware (for speed-up) with processor-memory architectures. Such hardware can execute many functions in parallel, leading to a limited parallel system where a single software process can execute on the processor at any time, in parallel with a number of functions implemented on the reconfigurable hardware. This approach is not amenable to conventional fixed priority timing analysis, as fundamental assumptions are compromised, namely that of a critical instant. This paper describes generalised fixed priority timing analysis for limited parallel systems, illustrated by an example system utilising field programmable gate arrays as the reconfigurable hardware resource.

DOI: 10.1109/RTTAS.2004.1317285

Cite this paper

@article{Audsley2004RealisticAO, title={Realistic analysis of limited parallel software/hardware implementations}, author={Neil C. Audsley and Konstantinos Bletsas}, journal={Proceedings. RTAS 2004. 10th IEEE Real-Time and Embedded Technology and Applications Symposium, 2004.}, year={2004}, pages={388-395} }