Realistic Workload Characterization and Analysis for Networks-on-Chip Design

Abstract

As silicon device scaling trends have simultaneously increased transistor density while reducing component costs, architectures incorporating multiple communicating components are becoming more common. In these systems, networks-on-chip (NOCs) connect the components for communication and NOC design is critical to the performance and efficiency of the system… (More)

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Cite this paper

@inproceedings{Gratz2009RealisticWC, title={Realistic Workload Characterization and Analysis for Networks-on-Chip Design}, author={Paul V. Gratz and Stephen W. Keckler}, year={2009} }