Hardware-accelerated analysis of real-time Networks-on-Chip
Many state-of-the-art approaches to power minimisation in Networks-on-Chip (NoC) are based on the reduction of the communication paths taken by packets over the interconnect. This is often done by optimising the packet routing, the allocation of tasks that produce and consume those packets, or both. In all cases, the optimisation affects the timeliness of the packets, because changes will occur in the way resources are shared at the platform cores (as tasks are reallocated) and NoC links (as packet routes are changed). In this paper, we propose an optimisation technique that is able to minimise power dissipation without sacrificing timing constraints, thus suitable to systems with hard real-time requirements. It is based on a Genetic Algorithm (GA) that evolves chromosomes representing the mapping of tasks to cores, guided by a multi-objective fitness function that combines power estimation macromodels and real-time schedulability analysis.