Corpus ID: 13553706

Real-Time Wideband Telemetry Receiver Architecture and Performance

  title={Real-Time Wideband Telemetry Receiver Architecture and Performance},
  author={K. Andrews and J. Gin and Norman E. Lay and K. Quirk and M. Srinivasan},
  • K. Andrews, J. Gin, +2 authors M. Srinivasan
  • Published 2006
  • Computer Science
  • We describe the architecture and algorithm development for a field programmable gate array (FPGA) wideband telemetry receiver prototype capable of processing data rates in excess of 100 megabits per second (Mbps). The high-speed parallel implementations of the matched filter, carrier phase tracking loop, and symbol timing recovery loop are discussed, along with simulation and hardware performance results. 
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